From Vice Chancellors’s Desk

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“At GEHU, we deliver world-class education while shaping our students into skilled professionals and excellent leaders. By embracing AI-driven learning, fostering adaptability and equipping students with future-ready skills, we prepare them to excel in a rapidly evolving world.”

Prof. (Dr.) Amit R. Bhatt

Vice Chancellor, Graphic Era Hill University

Graphic Era Hill University (GEHU) stands as a beacon of academic excellence, driven by the visionary leadership of our Founder, Prof. (Dr.) Kamal Ghanshala, and a relentless pursuit of knowledge, innovation and holistic development. At GEHU, we take pride in nurturing value-driven individuals, competent professionals, and future leaders. Our commitment to excellence is reflected in our world-class infrastructure, industry-aligned curriculum and emphasis on research, artificial intelligence, and technological innovation. Through strategic collaborations with global industry leaders like IBM, Adobe, Infosys and Capgemini, along with academic exchanges with prestigious institutions worldwide, we equip our students with unparalleled global exposure. With AI-driven learning methodologies and state-of-the-art labs, we empower students to harness the potential of emerging technologies. The university fosters an inclusive, diverse and vibrant learning environment where students are encouraged to think innovatively, challenge norms, and develop leadership and teamwork skills. Our graduates consistently achieve remarkable success, securing positions in top corporations such as Apple, Microsoft, Google, Amazon and Tata Technologies, reinforcing our reputation as a premier institution.

At GEHU, education is more than just academics—it’s about shaping character, building resilience and inspiring dreams. We are deeply committed to instilling ethical values, social responsibility and a strong Indian ethos in our students, preparing them to make a meaningful impact on society. With AI integration in curriculum design, smart learning analytics and hands-on projects in machine learning and automation, we ensure that our students stay ahead in an evolving digital world. Our “question-by-example” approach to learning cultivates curiosity, adaptability and self-improvement, ensuring our students excel not just in their careers but also as responsible global citizens. With a thriving alumni network and an ever-growing legacy of excellence, we continue to evolve, driven by our mission to empower students with knowledge, skills and values. The future is bright, and we look forward to shaping it together—one success story at a time.

Qualifications:

PhD (EE) in Semiconductor Quantum Devices, North Carolina State University USA (1991-1995)
MS(EE) in Computer Architecture, Duke University, USA (1989- 1990)
BE in Electrical Engineering, M. S. University of Baroda (1981 – 1985)

Areas of Technical Expertise:

General Purpose and AI accelerator Processor Design, Machine Learning (ML) and Artificial Intelligence (AI) on “Edge Devices”, Internet of Things (IoT or Industry 4.0), VLSI design Hardware/Software co-design issues
Experience of working in Academia and Industries both in India and abroad and forming mutually beneficial collaborative programs.
Working with the Government / international agencies in framing the policy on IT and Electronics
Excellent communication skills with good command over English, Gujarati and Hindi languages

Position Held:

DSU Pro Vice-Chancellor & Officiating Vice-Chancellor (January 2023-present)

Complete curriculum overhaul with common curriculum for the first two years across all engineering streams. Strong emphasis on Mathematics education – which is the foundation of all computer science and ECE branches and for AI/ML related courses.
Improved industry participation in the Board of Studies of various Engineering branches to keep the curriculum up to date.
Improved research output by 25% in two years
Formed Special Interest Groups (SIGs) among faculty members to align with university priorities
Supervised design and infrastructure requirement for state of the art Centers of Excellence labs
Created industry connects with top Hitech MNCs and cuttingedge startups
Improved admission and placement statistics
Nurtured Center for Space Science & Technology (CSST) to build 3U satellite – with first launch in 2025.
Developed a framework for faculty promotion policy and welfare activities. Proposed streamlined system and procedures for the smooth operations
Overseen first NAAC application in which DSU achieved A+ grade
Worked with the International Affairs department to increase foreign students’ intake and promote regular faculty exchange.

DAIICT (2011 – 2022): Professor and a Consultant in the areas of processor/SoC development, Machine Learning & AI, IoT, Electronics Eco-system and Telecom Policy issues.

Team leader in getting DAIICT selected as an “Anchor Institute” in the area of ICT under the Anchor Institute Program Scheme announced by the Center of Entrepreneurship Development (CED) – Department of Industry and Mines. Anchor Institute gets a grant of 10 crors to be used over 5 years. DAIICT as an anchor institute would be responsible for training students and faculty members of Gujarat state in the industry standard skill set
Founded a startup called “Treepie Computing” involved in cluster computing using low power mobile chipsets. It was judged as a top ten startup and special funding was provided by the jury having members from Qualcomm and NASSCOM
Qualcomm (External Consultant): Special lectures and training sessions on Processor Architecture, ARM ISA, Advanced electronics and current trends in mobile processors at Bangalore and Hyderabad sites
Invited member of the ITU-T (International Telecommunication Union) focus group on innovations
Consultant to the Telecom Center of Excellence at IIM-A (Indian Institute of Management – Ahmadabad) on “Mobile Eco-system” and ICT patent issues

ARM (Aug 2007 – Dec 2010) Manager – Technology Enablement, CTO office

To identify, define and Promote relevant ARM technology to the Industry partners and Academia
To keep track of announcements and innovations in the area of mobile computing
To be a bridge between R&D and Engineering divisions
Make engineering divisions in Bangalore aware about the activities of worldwide ARM R&D activities
Present and promote ARM technology in universities around the world
Keep track of research in being carried out in the universities

Cadence (Aug – 2006, July 2007) Engineering Manager – RC Front end tool

Duties involved – solving the problematic cases and bugs referred through from the field engineers. Suggesting possible steps to solve it or refer it to the R&D division with recommendations on changes to the RC tool.
Mentoring to the younger members of the team and teach them how to isolate the problem using the right test cases
Suggest a new algorithm for insertion of scan chain for test purpose – was taken up by San Jose center for detailed analysis. Suggested two power and device saving tricks for implementation in the RC Tool

University of Illinois at Urbana-Champaign: Fulbright Visiting Scholar

DAIICT (2001 – 2006) Associate Professor

One of the founding faculty member of DAIICT
Developed Digital VLSI and computer architecture department from .scratch
PG coordinator in 2002 -2003 and other administrative duties
Guided 37 PG students and 80+ UG students in thesis and final projects
Three projects by UG students won prizes at Intel, Cadence and TI competition

Visiting Professor to SVIT (Vasad) and Nirma Institute of Technology (1998 – 2001)

Publications:

[ Includes some of the important papers and important invited talks. MTech & BTech Student authored papers not included. Work done while in industry and consultancy projects not cited, talks given for FDP in various institutes of India not cited.]

A. Mankodi, A. Bhatt, and B. Chaudhury, “Performance prediction from simulation systems to physical systems using machine learning with transfer learning and scaling,” Concurrency and Computation: Practice and Experience, p. E6433, jun 2021. tps://www.doi.org/10.1002/cpe.6433)
A. Mankodi, A. Bhatt, and B. Chaudhury, “Multivariate Performance and Power Prediction of Algorithms on Simulation-Based Hardware Models,” in 2020 19th International Symposium on Parallel and Distributed Computing (ISPDC), Warsaw, Poland, pp. 150–157, IEEE, jul 2020. (https://www.doi.org/10.1109/ISPDC51135.2020.00029)
A. Mankodi, A. Bhatt, and B. Chaudhury, “Evaluation of neural network models for performance prediction of scientific applications,” in IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 2020-Novem, Osaka, Japan, pp. 426–431, Institute of Electrical and Electronics Engineers Inc., nov 2020. (https://www.doi.org/10.1109/TENCON50793.2020.9293788)
A. Mankodi, A. Bhatt, and B. Chaudhury, “Performance Prediction of Physical Computer Systems Using Simulation-Based Hardware Models,” in 2020 International Conference on High Performance Big Data and Intelligent Systems, HPBD and IS 2020, (Beijing), pp. 1–5, Chinese Academy of Sciences, IEEE, Beijing, China, may 2020. (https://www.doi.org/10.1109/HPBDIS49115.2020.9130599)
A. Mankodi, A. Bhatt, B. Chaudhury, R. Kumar, and A. Amrutiya, “Evaluating Machine Learning Models for Disparate Computer Systems Performance Prediction,” in 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, pp. 1–6, IEEE, jul 2020. (https://www.doi.org/10.1109/CONECCT50063.2020.9198512)
A. Mankodi, A. Bhatt, B. Chaudhury, R. Kumar, and A. Amrutiya, “Modeling Performance and Power on Disparate Platforms Using Transfer Learning with Machine Learning Models,” in Proceedings of CoMSO 2020 – Modeling, Simulation and Optimization, NIT Silchar, India, pp. 231–246, Springer, 2021. (https://www.doi.org/10.1007/978-981-15-9829-6_18)
R. Kumar, A. Mankodi, A. Bhatt, B. Chaudhury, and A. Amrutiya, “CrossPlatform Performance Prediction with Transfer Learning using Machine Learning,” in 2020 11th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2020, Institute of Electrical and Electronics Engineers Inc., IIT Kharagpur, India, jul 2020. (https://www.doi.org/10.1109/ICCCNT49239.2020.9225281)
A. Mankodi, A. Bhatt, and B. Chaudhury, “Learning Based Performance Prediction of Algorithms on Disparate Computer Hardware Models.”, submitted in February 2021 to Transactions on Modeling and Performance Evaluation of Computing Systems, ACM [Journal Since 2016, Average Citation: 3, 100 Paper Publishes, 332 Citations] First Review Submitted on 11-Mar-2022, Waiting for Decision
A. Mankodi, A. Bhatt, and B. Chaudhury, “Predicting Physical Computer Systems Performance and Power from Simulation-Based Hardware using Machine Learning Model., submitted in April 2021 to Computing Special Issue, Springer[Journal Impact Factor: 2.06] March 2022. https://doi.org/10.1007/s00607-022-01066-5
A. Mankodi, H. Suthar, and A. Bhatt, “Application-Based Evaluation of Neural Network Architectures for Edge Devices,” in 2021 International Conference on Advanced Network Technologies and Intelligent Computing, Institute of Science Banaras Hindu University, India
Invited talk on “Machine Learning on ARM processors” at the Department of Computer Science, Obuda University, Budapest, Hungary, 14th March, 2019
Invited talk on “Machine Learning on ARM processors (edge computing)” at the Aurel Vlaicu University, Arad, Romania on 11th of March, 2019
Invited talk on “Machine Learning and Deep learning techniques on ARM processors (edge computing)” at the University of Vienna, Vienna, Austria on 9th March, 2019
Qualcomm sponsored invited paper on “HPC using Cellphone chips” at the International conference on VLSI and Embedded systems, Bangalore, 6th January, 2015
Report on “the Critique of India’s Electronic Policy” supported by IITCOE – IIMA. Submitted (August, 2015)
Keynote speech on “Democratization of HPC” at Nirma University (Nov 2014)
Keynote speech on “ARM vs INTEL: Battle of Architecture” at Pondicherry Engineering College (Sept, 2014)
Invited lecture on “ITRS road map and future of computing” at CHARUSAT UNIVERSITY and Marwari Institute (Aug, 2014)
Published a report on “Patents regime in ICT” for for IIM-A and TCOE center (August 2013)
Invited talk at CDNLive conference, Munich Germany on “Facilitating VLSI education in India” (Sept 2012)
Published a report on “Mobile Telecomm Ecosystem” for IIM-A and TCOE center (Nov, 2011)
Invited IETE talk at IT-BHU on multicore architecture Aug 2010
Invited talk, ARM -Cambridge, on “Physics behind the ITRS roadmap” Aug 2010
Presentation at University of Michigan and ARM R&D joint session in Austin on “Thermal Issues in 3D IC design” July 2010
Internal ARM note on “Multigate devices and its impact on ARM processors” March 2010
Special presentation to ARM-SanJose center on “advanced semiconductor devices” January 2010
Talk at Nanyang Technical University on ARM architecture November 2009
Invited talk, International VLSI & Embedded systems conference, Bangalore on “ARM Multicore architecture” January 2008
Invited talk, MSRSAS, “ARM virtualization technology” February 2009
Invited talk, Manipal Institute of Technology “ARM workshop” on future of embedded processors Nov 2008
Invited talk, CDAC – Hyderabad “Impact of CMSIS on embedded computing” Dec 2007
Design of reconfigurable, application specific instruction set processor for Kalman filter – with Kinjal Dave (Dec 2005)
Conceived and designed a low cost image processing system requiring a low bandwidth for the distance education program for rural schools with five BTech students (INTEL award) (2006)
Designed and implemented a Novel architecture for EBC in JPEG 2000. Published and delivered lecture in VLSI 2006 conference (2005)
Designed a 32 bit RISC like processor with a team of 6 final year BTech students, which was meant to be used as a test case for cache optimization research – accepted by Cadence as a student reference design (2003)
A. R. Bhatt, K. W. Kim, M. A. Stroscio, and J. M. Higman, “Simplified Microscopic Model for Electron-Optical-Phonon Interactions in Quantum Wells,” Phys. Rev. B 48, 14671 (1995).
A. R. Bhatt, K. W. Kim, and M. A. Stroscio, “Theoretical Calculation of Lifetimes for GaAs and GaP,” presented at the March Meeting of the American Physical Society (March, 1994, Pittsburgh, Penn.), Bull. Am. Phys. Soc. 39, 397 (1994).
A. R. Bhatt, K. W. Kim, M. A. Stroscio, G. J. Iafrate, M. Dutta, H. L. Grubin, R. Haque, and X. T. Zhu, “Reduction of Interface Phonon Modes Using MetalSemiconductor Heterostructures,” J. Appl. Phys. 73, 2338 (1993).
A. R. Bhatt, K. W. Kim, and M. A. Stroscio, “Theoretical Calculation of Longitudinal-Optical Phonon Lifetime in GaAs,” J. Appl. Phys. 76, 3905 (1994).
A. R. Bhatt, K. W. Kim, M. A. Stroscio, P. J. Turley, and S. W. Teitsworth, “Effects of Interface Phonon Scattering in Multi-Heterointerface Structures,” J. Appl. Phys. 72, 2282 (1992).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, M. A. Littlejohn, A. R. Bhatt, and M. Dutta, “Confined and Interface Phonons in Quantum Wells and Quantum Wires,” presented at the 2nd Workshop on Optical Properties of Mesoscopic Semiconductor Structures (April, 1993, Snow Bird, Utah).
A. R. Bhatt, M. A. Stroscio, K. W. Kim, G. J. Iafrate, M. Dutta, and H. L. Grubin, “Reduction of Inelastic Longitudinal-Optical Phonon Scattering in Narrow PolarSemiconductor Quantum Wells,” Proc. SPIE 1675, 237 (1992).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, A. R. Bhatt, M. Dutta, and H. L. Grubin, “Reduction in Longitudinal-Optical Phonon Emission Rate in PolarSemiconductor Quantum Wires and Quantum Wells,” in Phonon Scattering in Condensed Matter VII, edited by M. Meissner and R. O. Pohl (Springer-Verlag, Berlin, 1993), Springer Series in Solid-State Sciences, Vol.112, p. 341.
M. A. Stroscio, G. J. Iafrate, K. W. Kim, M. A. Littlejohn, A. R. Bhatt, and M. Dutta, “Confined and Interface Optical Phonons in Quantum Wells and Quantum Wires,” Proc. SPIE CR45, 341 (1993).
A. R. Bhatt, M. A. Stroscio, K. W. Kim, G. J. Iafrate, M. Dutta, and H. L. Grubin, “Reduction of Inelastic Longitudinal-Optical Phonon Scattering in Narrow PolarSemiconductor Quantum Wells,” presented at the SPIE Symp. on Compound Semiconductor Physics and Devices (March, 1992, Somerset, New Jersey).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, A. R. Bhatt, M. Dutta, and H. L. Grubin, “Reduction in Longitudinal-Optical Phonon Emission Rate in PolarSemiconductor Quantum Wires and Quantum Wells,” presented at the 7th Intl. Conf. on Phonon Scattering in Condensed Matter (August, 1992, Ithaca, New York).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, M. A. Littlejohn, A. R. Bhatt, and M. Dutta, “Confined and Interface Optical Phonons in Quantum Wells and Quantum Wires (Invited),” presented at the SPIE Intl. Symp. on Optoelectronic Packaging and Interconnects (January, 1993, Los Angeles, Calif.).
A. R. Bhatt, K. W. Kim, and M. A. Stroscio, “Microscopic Model for Confined and Interface Longitudinal Optical Phonons in Polar Semiconductor Nanostructures,” presented at the March Meeting of the American Physical Society (March, 1993, Seattle, Washington), Bull. Am. Phys. Soc. 38, 269 (1993).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, A. R. Bhatt, M. Dutta, and C.-J. Chiu, “Interface Longitudinal Optical Phonon Modes in Polar semiconductor Nanostructures,” presented at the March Meeting of the American Physical Society (March, 1993, Seattle, Washington), Bull. Am. Phys. Soc. 38, 55 (1993).
M. A. Stroscio, G. J. Iafrate, K. W. Kim, M. A. Littlejohn, A. R. Bhatt, and M. Dutta, “Confined and Interface Phonons in Quantum Wells and Quantum Wires,” presented at the 2nd Workshop on Optical Properties of Mesoscopic Semiconductor Structures (April, 1993, Snow Bird, Utah).